1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to suppression of data retention failure of a nonvolatile semiconductor memory device having a memory cell array of a stacked gate structure having a floating gate.
2. Description of the Related Art
An EEPROM (Electrically Erasable and Programmable Read Only Memory) capable of electrically writing and erasing information is known as one of nonvolatile memories. Moreover, among EEPROMs, in a NAND-type flash EEPROM suitable for high integration, a plurality of memory transistors are connected in series in a manner that respective sources and drains are shared between adjacent ones, the serially connected memory transistors are connected as one unit to a bit line. Thus data is deleted all at once.
FIG. 1 is a partial cross section view of a device, showing structures of a memory cell region 100 and a peripheral circuit region 200 of a conventional NAND-type flash EEPROM. As shown in the drawing, in the memory cell region 100, transistors of a stacked gate structure, in which a gate oxide film 114, a floating gate electrode 116, an insulating film between gates 118 and a control gate 120 are stacked upward in this order, are formed in arrays and source/drain diffusion regions 112 are formed in a Si substrate 110 below both sides of each gate.
In the peripheral circuit region 200, a transistor element and the like for a power supply circuit and the like are formed as necessary. Usually, this transistor element has a single layer gate structure, in which, for example, a gate electrode 116b is formed in the same layer as a conductive layer constituting the floating gate electrode 116 of the memory cell region 100 and source/drain regions 112b are formed in the semiconductor substrate layer at both sides thereof.
Furthermore, on the memory cell region 100 and peripheral circuit region 200, necessary contacts (126 and 140) and wirings (130, 136 and 142) are formed with a plurality of interlayer insulating films (124, 128, 134 and 138) interposed therebetween and a passivation layer is formed on the resultant structure. The passivation layer is often formed of multiple layers. For example, a SiO2 film with a good covering property is formed as a first passivation film 144 of a lower layer, and a SiNx film hardly moisture permeable is formed as a second passivation film 146 of an upper layer. In order to secure moisture resistance and the like, such passivation films are indispensable components for the nonvolatile semiconductor memory device.
When writing data into each cell, predetermined voltages are applied to the drain region 112 and the control gate electrode 120. Along with the application of voltages, a tunnel current flowing from the drain region 112 to the floating gate electrode 116 via the gate insulating film 114 is generated, by injecting electrons into the floating gate electrode 116.
In an EEPROM which performs a storage operation of binary data, for example, when a threshold voltage Vth of a memory cell is a predetermined value or more due to electrons injected and accumulated in the floating gate electrode 116, state “0” is established.
Moreover, when the control gate electrode 120 is set to a ground potential, and the drain region 112 is set in its floating state, the electrons in the floating gate electrode 116 are extracted via the gate insulating film 114 due to a voltage applied to the source region 112. Thus the threshold voltage Vth of the memory cell transistor is lowered. Such a state where the threshold voltage becomes lower than the predetermined value is state “1.”
When reading out the data of each cell, “0” and “1” are read out depending on the presence of the flow of the current by the threshold voltage Vth corresponding to a state of each piece of the data.
In general, to form passivation films, a plasma CVD method is utilized, which is relatively low in a deposition temperature. Furthermore, gas containing hydrogen is used as a gas material, such as monosilane (SiH4) gas, TEOS (Si(OC2H5)4) gas and the like. Thus, a large amount of hydrogen tends to be contained in the passivation films. The hydrogen contained in the films tends to be diffused even in a heat treatment with a relatively low temperature. In some cases, the hydrogen is diffused in an assembly process and the like following after a passivation film formation process and reaches a transistor region of the memory cell.
The hydrogen that has reached the floating gate electrode 116 or the gate insulating film 114 forms a trap level for electrons there. Therefore, in writing/erasing of data in each memory cell, there is a risk that the trap level caused by the diffused hydrogen brings about a fluctuation of the threshold voltage Vth. Furthermore, this fluctuation of Vth becomes a factor causing data retention (a data retention property) failure.
Meanwhile, for miniaturization of a pattern upon demand of much higher integration, in the NAND-type flash EEPROM, an influence of a variation in processing accompanied with the miniaturization on the number of times of writing/erasing has been no longer negligible. Thus, a margin for the data retention failure has been decreased.
Furthermore, recently, an EEPROM storing multi-value data of three different values or more in each memory cell has been put into practical use for achieving a larger memory capacity, aside from the one performing the conventional binary data storage operation of “1” and “0.” However, in the case of dealing with such multi-value data, an allowable breadth of a threshold value distribution is made narrower than that in the conventional binary data storage operation, thus leading to a situation where the data retention failure far more tends to occur.